1. Technical Field of the Present Invention
The present invention generally relates to integrated circuits and embedded memory and, more specifically, to Built-In Self Test circuitry that repairs the embedded memory during operation of the integrated circuit.
2. Description of Related Art
Integrated circuits are increasingly relying upon larger amounts of embedded memory to meet functional and performance demands. The memory typically covers a significant area of the integrated circuit and, consequently, is subject to a number of potential defects (e.g., shorts, surface and the like). If any portion of the memory is defective the integrated circuit is inoperable or unreliable.
As part of the manufacturing process to increase yield, redundant memory elements are included that can be selectively interchanged with defective memory elements using repair registers and fuses. The fuses are used to store the information concerning the redundant memory elements and the defective memory elements they replace. During operation of the integrated circuit, this information is retrieved and loaded into repair registers such that the redundant memory elements are accessed in lieu of the corresponding defective memory elements.
A Built-In Self Test (BIST) and a Built-In Redundancy Analyzer (BIRA) are typically used to perform in-system testing and replacement of defective memory elements. The BIST is responsible for providing the necessary controls and stimuli to the memory during testing. The BIRA monitors the testing for any errors that indicate a defective memory element (e.g., a mismatch on a write/read combination) and performs the blowing of fuses or other means for indicating the redundant element that is to replace the defective memory element.
During operation of the integrated circuit, advanced memory controllers can typically identify a failing memory address. As a result of this identification, the memory controller will instruct the BIST to perform an in-system test on the memory and, hopefully, find and repair the defect. The BIST performs the in-system test using stimuli patterns for the entire addressing scheme of the memory. Unfortunately, this process may fail to properly identify the previous failing memory address due to pattern limitations and the like.
It would, therefore, be a distinct advantage to have a method and apparatus that provides a BIST that is capable of receiving a failing memory address directly from the memory controller and replacing the defective memory element using that address.